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OPS8085.ARI
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1987-05-05
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901 lines
% Subject: OPS8085.ARI - from A. Lane: "Simulating an 8085 with Prolog"
comp_regs(Regname) :-
retract(state(R,PC,SP,_)),
reg(Regname,Place),
arg(Place,R,Reg),
X is A - Reg,
adjust_flags(A,X,_,Flags),
asserta(state(R,PC,SP,Flags)).
acc_math_with_carry(Op,Regname) :-
retract(state(R,PC,SP,flags(_,_,_,CY,_))), % get what we need
arg(1,R,A), % extract A from R
reg(Regname,Place), % Place is location of Regname in R
arg(Place,R,Reg), % extract register value
T1 =.. [Op,Reg,CY], % set up additions/subtractions
T2 =.. [Op,A,T1],
X is T2, % evaluate
adjust_flags(A,X,Y,Flags), % adjust for flags
argrep(R,1,Y,NewR), % replace register value in R
asserta(state(NewR,PC,SP,Flags)).
acc_math(Op,Regname) :-
retract(state(R,PC,SP,_)),
arg(1,R,A),
reg(Regname,Place), arg(Place,R,Reg),
T1 =.. [Op,A,Reg],
X is T1,
adjust_flags(A,X,Y,Flags),
argrep(R,1,Y,NewR),
asserta(state(NewR,PC,SP,Flags)).
reg_math(Op,Regname) :-
retract(state(R,PC,SP,flags(_,_,_,CY,_))), arg(1,R,A),
reg(Regname,Place), % Place is location of Regname in R
arg(Place,R,Reg), % extract register value
T1 =.. [Op,Reg,TemReg],% take advantage of Arity inc() and dec()
call(T1),
adjust_flags(A,TemReg,NewReg,flags1(Z,S,P,_,AC)),
argrep(R,1,NewReg,NewR), % replace register value in R
asserta(state(NewR,PC,SP,flags(Z,S,P,CY,AC))).
not_implemented. % some things are not worth doing.
undefined.
move(mem, mem).
move(mem,D) :-
retract(state(R,PS,SP,F)),
arg(6,R,H),
arg(7,R,L),
get_mem(H,L,Data),
argrep(R,D,Data,NewR),
asserta(state(NewR,PC,SP,F)).
move(S,mem) :-
state(R,PS,SP,F),
arg(6,R,H),
arg(7,R,L),
arg(S,R,Data),
put_mem(H,L,Data).
move( S,D ) :-
retract(state(R,P,SP,F)),
arg(S,R,S1),
argrep(R,D,S1,NewR),
asserta(state(NewR,P,SP,F)).
reg_ptr(6,mem).
reg_ptr(A,B) :- B is (A + 2) mod 8.
op(0). /* NOP */
op(1) :- /* LXI BC */
retract(state(regs(A,_,_,D,E,H,L),PC,SP,Flags)),
get_mem(PC,C), Hi is PC + 1,
get_mem(Hi,B),
NewPC is PC + 2,
asserta(state(regs(A,B,C,D,E,H,L),NewPC,SP,Flags)).
op(2) :- /* STAX B */
state(regs(A,B,C,_,_,_,_),_,_,_),
put_mem(B,C,A).
op(3) :- /* INX B */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)),
BC is 256 * B + C + 1,
decompose(BC,NewB,NewC),
asserta(state(regs(A,NewB,NewC,D,E,H,L),PC,SP,Flags)).
op(4) :- reg_math(inc,b),!. /* INR B */
op(5) :- reg_math(dec,b),!. /* DCR B */
op(6) :- /* MVI B, data */
retract(state(regs(A,_,C,D,E,H,L),PC,SP,Flags)),
get_mem(PC,B),
NewPC is PC + 1,
asserta(state(regs(A,B,C,D,E,H,L),NewPC,SP,Flags)).
op(7) :- /* RLC */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,flags(Z,S,P,_,AC))),
CY is A mod 128,
A1 is (2 * A + CY) mod 256,
asserta(state(regs(A1,B,C,D,E,H,L),PC,SP,flags(Z,S,P,CY,AC))).
op(9) :- /* DAD B (CY only)*/
retract(state(regs(A,B,C,D,E,H,L),PC,SP,flags(Z,S,P,_,AC))),
NewL is L + C,
Carry is NewL // 256,
NewH is H + B + Carry,
CY is NewH // 256,
FL is NewL /\ 255,
FH is NewH /\ 255,
asserta(state(regs(A,B,C,D,E,FH,FL),PC,SP,flags(Z,S,P,CY,AC))).
op(10) :- /* LDAX B */
retract(state(regs(_,B,C,D,E,H,L),PC,SP,Flags)),
get_mem(B,C,A),
asserta(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)).
op(11) :- /* DCX B */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)),
BC is 256 * B + C - 1,
decompose(BC,B1,C1),
asserta(state(regs(A,B1,C1,D,E,H,L),PC,SP,Flags)).
op(12) :- reg_math(inc,c),!. /* INR C */
op(13) :- reg_math(dec,c),!. /* DCR C */
op(14) :- /* MVI C, data */
retract(state(regs(A,B,_,D,E,H,L),PC,SP,Flags)),
get_mem(PC,C),
NewPC is PC + 1,
asserta(state(regs(A,B,C,D,E,H,L),NewPC,SP,Flags)).
op(15) :- /* RRC */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,flags(Z,S,P,_,AC))),
CY is A mod 2,
I1 is CY * 128,
A1 is A // 2 + I1,
asserta(state(regs(A1,B,C,D,E,H,L),PC,SP,flags(Z,S,P,CY,AC))).
op(17) :- /* LXI DE */
retract(state(regs(A,B,C,_,_,H,L),PC,SP,Flags)),
memory(PC,E),
Hi is PC + 1,
memory(Hi,D),
NewPC is PC + 2,
asserta(state(regs(A,B,C,D,E,H,L),NewPC,SP,Flags)).
op(18) :- /* STAX D */
state(regs(A,_,_,D,E,_,_),_,_,_),
put_mem(D,E,A).
op(19) :- /* INX D */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)),
DE is 256 * D + E + 1,
D1 is DE // 256,
E1 is DE mod 256,
asserta(state(regs(A,B,C,D1,E1,H,L),PC,SP,Flags)).
op(20) :- reg_math(inc,d),!. /* INR D */
op(21) :- reg_math(dec,d),!. /* DCR D */
op(22) :- /* MVI D, data */
retract(state(regs(A,B,C,_,E,H,L),PC,SP,Flags)),
memory(PC,D),
NewPC is PC + 1,
asserta(state(regs(A,B,C,D,E,H,L),NewPC,SP,Flags)).
op(23) :- /* RAL */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,flags(Z,S,P,CY,AC))),
A1 is (2 * A + CY) mod 256,
NewCY is A mod 128,
asserta(state(regs(A1,B,C,D,E,H,L),PC,SP,flags(Z,S,P,NewCY,AC))).
op(25) :- /* DAD D */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,flags(Z,S,P,_,AC))),
NewL is L + E,
Carry is NewL // 256,
NewH is H + D + Carry,
CY is NewH // 256,
FL is NewL /\ 255,
FH is NewH /\ 255,
asserta(state(regs(A,B,C,D,E,FH,FL),PC,SP,flags(Z,S,P,CY,AC))).
op(26) :- /* LDAX D */
retract(state(regs(_,B,C,D,E,H,L),PC,SP,Flags)),
get_mem(D,E,A),
asserta(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)).
op(27) :- /* DCX D */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)),
DE is 256 * D + E - 1,
decompose(DE,D1,E1),
asserta(state(regs(A,B,C,D1,E1,H,L),PC,SP,Flags)).
op(28) :- reg_math(inc,e),!. /* INR E */
op(29) :- reg_math(dec,e),!. /* DCR E */
op(30) :- /* MVI E, data */
retract(state(regs(A,B,C,D,_,H,L),PC,SP,Flags)),
get_mem(PC,E),
NewPC is PC + 1,
asserta(state(regs(A,B,C,D,E,H,L),NewPC,SP,Flags)).
op(31) :- /* RAR */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,flags(Z,S,P,CY,AC))),
A1 is (A // 2) + (128 * CY),
NewCY is A mod 2,
asserta(state(regs(A1,B,C,D,E,H,L),PC,SP,flags(Z,S,P,NewCY,AC))).
op(32) :- /* RIM (read interrupt mask) */
not_implemented.
op(33) :- /* LXI HL */
retract(state(regs(A,B,C,D,E,_,_),PC,SP,Flags)),
get_mem(PC,L),
Hi is PC + 1,
get_mem(Hi,H),
NewPC is PC + 2,
asserta(state(regs(A,B,C,D,E,H,L),NewPC,SP,Flags)).
op(34) :- /* SHLD (store H L direct) */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)),
get_mem(PC,Lo), NextPC is PC + 1,
get_mem(NextPC,Hi),
put_mem(Hi,Lo,L), NextLo is Lo + 1,
put_mem(Hi,NextLo,H),
NewPC is PC + 2,
asserta(state(regs(A,B,C,D,E,H,L),NewPC,SP,Flags)).
op(35) :- /* INX H */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)),
HL is 256 * H + L + 1,
decompose(HL,H1,L1),
asserta(state(regs(A,B,C,D,E,H1,L1),PC,SP,Flags)).
op(36) :- reg_math(inc,h),!. /* INR H */
op(37) :- reg_math(dec,h),!. /* DCR H */
op(38) :- /* MVI H, data */
retract(state(regs(A,B,C,D,E,_,L),PC,SP,Flags)),
get_mem(PC,H),
NewPC is PC + 1,
asserta(state(regs(A,B,C,D,E,H,L),NewPC,SP,Flags)).
op(39) :- /* DAA */
state(regs(A,B,C,D,E,H,L),_,_,flags(Z,S,P,CY,AC)),
LSB is A /\ 15,
LSB > 9;
AC is 1, !, retract(state(_,PC,SP,F)),
NewA is A + 6,
asserta(state(regs(NewA,B,C,D,E,H,L),PC,SP,F)),
MSB is NewA /\ 240,
MSB > 9;
CY is 1, !, retract(_,PC,_,_),
FinalA is NewA + 6,
asserta(state(regs(FinalA,B,C,D,E,H,L),PC,SP,F)).
op(41) :- /* DAD H */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,flags(Z,S,P,_,AC))),
NewL is L + L, % sum L plus lo-order register
Carry is NewL // 256, % Carry is one if NewL > 255
NewH is H + H + Carry, % sum H with hi-order register
CY is NewH // 256, % CY flag is one if NewH > 255
FL is NewL /\ 255, % bring into byte range
FH is NewH /\ 255, % this one too
asserta(state(regs(A,B,C,D,E,FH,FL),PC,SP,flags(Z,S,P,CY,AC))).
op(42) :- /* LHLD (load H L direct) */
retract(state(regs(A,B,C,D,E,_,_),PC,SP,Flags)),
get_mem(PC,Lo), NextPC is PC + 1,
get_mem(NextPC,Hi),
get_mem(Hi,Lo,L), NextLo is Lo + 1,
get_mem(Hi,NextLo,H),
NewPC is PC + 2,
asserta(state(regs(A,B,C,D,E,H,L),NewPC,SP,Flags)).
op(43) :- /* DCX H */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)),
HL is 256 * H + L - 1,
decompose(HL,H1,L1),
asserta(state(regs(A,B,C,D,E,H1,L1),PC,SP,Flags)).
op(44) :- reg_math(inc,l),!. /* INR L */
op(45) :- reg_math(dec,l),!. /* DCR L */
op(46) :- /* MVI L, data */
retract(state(regs(A,B,C,D,E,H,_),PC,SP,Flags)),
get_mem(PC,L),
NewPC is PC + 1,
asserta(state(regs(A,B,C,D,E,H,L),NewPC,SP,Flags)).
op(47) :- /* CMA (complement accumulator) */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)),
bit_xor(A,255,NewA),
asserta(state(regs(NewA,B,C,D,E,H,L),PC,SP,Flags)).
op(48) :- /* SIM (set interrupt mask) */
not_implemented.
op(49) :- /* LXI SP */
retract(state(Regs,PC,_,Flags)),
get_mem(PC,SPL),
Hi is PC + 1,
get_mem(Hi,SPH),
SP is 256 * SPH + SPL,
NewPC is PC + 2,
asserta(state(Regs,NewPC,SP,Flags)).
op(50) :- /* STA Adr (store accumulator in address) */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)),
get_mem(PC,Lo), HiAdr is PC + 1,
get_mem(HiAdr, Hi),
put_mem(Hi,Lo,A),
NewPC is PC + 2,
asserta(state(regs(A,B,C,D,E,H,L),NewPC,SP,Flags)).
op(51) :- /* INX SP */
retract(state(Regs,PC,SP,Flags)),
NewSP is SP + 1,
check_overflow(NewSP,FinalSP),
asserta(state(Regs,PC,FinalSP,Flags)).
op(52) :- /* INR M */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,flags(_,_,_,CY,_))),
get_mem(H,L,Data),
NewData is Data + 1,
adjust_flags(A,NewData,FinalData,flags1(Z,S,P,_,AC)),
put_mem(H,L,FinalData),
asserta(state(regs(A,B,C,D,E,H,L),PC,SP,flags(Z,S,P,CY,AC))).
op(53) :- /* DCR M */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,flags(_,_,_,CY,_))),
get_mem(H,L,Data),
NewData is Data - 1,
adjust_flags(A,NewData,FinalData,flags1(Z,S,P,_,AC)),
put_mem(H,L,FinalData),
asserta(state(regs(A,B,C,D,E,H,L),PC,SP,flags(Z,S,P,CY,AC))).
op(54) :- /* MVI M, data */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)),
get_mem(PC,Data),
put_mem(H,L,Data),
NewPC is PC + 1,
asserta(state(regs(A,B,C,D,E,H,L),NewPC,SP,Flags)).
op(55) :- /* STC (set carry) */
retract(state(Regs,PC,SP,flags(Z,S,P,_,AC))),
asserta(state(Regs,PC,SP,flags(Z,S,P,1,AC))).
op(57) :- /* DAD SP */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,flags(Z,S,P,_,AC))),
decompose(SP,SPH,SPL),
NewL is L + SPL,
Carry is NewL // 256,
NewH is H + SPH + Carry,
CY is NewH // 256,
FL is NewL /\ 255,
FH is NewH /\ 255,
asserta(state(regs(A,B,C,D,E,FH,FL),PC,SP,flags(Z,S,P,CY,AC))).
op(58) :- /* LDA Adr */
retract(state(regs(_,B,C,D,E,H,L),PC,SP,Flags)),
get_mem(PC,Lo),
NextPC is PC + 1,
get_mem(NextPC,Hi),
get_mem(Hi,Lo,A),
NewPC is PC + 2,
asserta(state(regs(A,B,C,D,E,H,L),NewPC,SP,Flags)).
op(59) :- /* DCX SP */
retract(state(Registers,PC,SP,Flags)),
NewSP is SP - 1,
check_overflow(NewSP,FinalSP),
asserta(state(Registers,PC,FinalSP,Flags)).
op(60) :- reg_math(inc,a),!. /* INR A */
op(61) :- reg_math(dec,a),!. /* DCR A */
op(62) :- /* MVI A, Data */
retract(state(regs(_,B,C,D,E,H,L),PC,SP,Flags)),
get_mem(PC,A),
NewPC is PC + 1,
asserta(state(regs(A,B,C,D,E,H,L),NewPC,SP,Flags)).
op(63) :- /* CMC (complement carry) */
retract(state(Regs,PC,SP,flags(Z,S,P,CY,AC))),
bit_xor(1,CY,NewCY),
asserta(state(Regs,PC,SP,flags(Z,S,P,NewCY,AC))).
op(Code) :- /* MOV Destination, Source */
Code > 63, Code < 128,
B210 is Code /\ 7, % decode which reg is in bits 0-2
B543 is (Code /\ 56) >> 3, % do same for bits 3-5
reg_ptr(B210,S),
reg_ptr(B543,D),
move(S,D).
op(128) :- acc_math(+,b),!.
op(129) :- acc_math(+,c),!.
op(130) :- acc_math(+,d),!.
op(131) :- acc_math(+,e),!.
op(132) :- acc_math(+,h),!.
op(133) :- acc_math(+,l),!.
op(134) :-
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
get_mem(H,L,Q),
X is A + Q,
adjust_flags(A,X,Y,Flags),
asserta(state(regs(Y,B,C,D,E,H,L),PC,SP,Flags)).
op(135) :- acc_math(+,a),!.
op(136) :- acc_math_with_carry(+,b),!. % add B with carry
op(137) :- acc_math_with_carry(+,c),!.
op(138) :- acc_math_with_carry(+,d),!.
op(139) :- acc_math_with_carry(+,e),!.
op(140) :- acc_math_with_carry(+,h),!.
op(141) :- acc_math_with_carry(+,l),!.
op(142) :-
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
get_mem(H,L,Q),
X is A + Q,
adjust_flags(A,X,Y,Flags),
asserta(state(regs(Y,B,C,D,E,H,L),PC,SP,Flags)).
op(143) :- acc_math_with_carry(+,a),!.
op(144) :- acc_math(-,b),!.
op(145) :- acc_math(-,c),!.
op(146) :- acc_math(-,d),!.
op(147) :- acc_math(-,e),!.
op(148) :- acc_math(-,h),!.
op(149) :- acc_math(-,l),!.
op(150) :-
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
get_mem(H,L,Q),
X is A + Q,
adjust_flags(A,X,Y,Flags),
asserta(state(regs(Y,B,C,D,E,H,L),PC,SP,Flags)).
op(151) :- acc_math(-,a),!.
op(152) :- acc_math_with_carry(-,b),!.
op(153) :- acc_math_with_carry(-,c),!.
op(154) :- acc_math_with_carry(-,d),!.
op(155) :- acc_math_with_carry(-,e),!.
op(156) :- acc_math_with_carry(-,h),!.
op(157) :- acc_math_with_carry(-,l),!.
op(158) :-
retract(state(regs(A,B,C,D,E,H,L),PC,SP,flags(_,_,_,CY,_))),
get_mem(H,L,Q),
X is A - Q - CY,
adjust_flags(A,X,Y,Flags),
asserta(state(regs(Y,B,C,D,E,H,L),PC,SP,Flags)).
op(159) :- acc_math_with_carry(-,a),!.
op(160) :- acc_math(/\,b),!.
op(161) :- acc_math(/\,c),!.
op(162) :- acc_math(/\,d),!.
op(163) :- acc_math(/\,e),!.
op(164) :- acc_math(/\,h),!.
op(165) :- acc_math(/\,l),!.
op(166) :-
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
get_mem(H,L,M),
X is A /\ M,
adjust_flags(A,X,Y,flags(Z,S,P,_,_)),
asserta(state(regs(Y,B,C,D,E,H,L),PC,SP,flags(Z,S,P,0,1))).
op(167) :- % AND A (affects flags)
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
adjust_flags(A,A,Y,flags(Z,S,P,_,_)),
asserta(state(regs(Y,B,C,D,E,H,L),PC,SP,flags(Z,S,P,0,1))).
op(168) :-
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
bit_xor(A,B,X),
adjust_flags(A,X,Y,flags(Z,S,P,_,_)),
asserta(state(regs(Y,B,C,D,E,H,L),PC,SP,flags(Z,S,P,0,0))).
op(169) :-
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
bit_xor(A,C,X),
adjust_flags(A,X,Y,flags(Z,S,P,_,_)),
asserta(state(regs(Y,B,C,D,E,H,L),PC,SP,flags(Z,S,P,0,0))).
op(170) :-
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
bit_xor(A,D,X),
adjust_flags(A,X,Y,flags(Z,S,P,_,_)),
asserta(state(regs(Y,B,C,D,E,H,L),PC,SP,flags(Z,S,P,0,0))).
op(171) :-
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
bit_xor(A,E,X),
adjust_flags(A,X,Y,flags(Z,S,P,_,_)),
asserta(state(regs(Y,B,C,D,E,H,L),PC,SP,flags(Z,S,P,0,0))).
op(172) :-
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
bit_xor(A,H,X),
adjust_flags(A,X,Y,flags(Z,S,P,_,_)),
asserta(state(regs(Y,B,C,D,E,H,L),PC,SP,flags(Z,S,P,0,0))).
op(173) :-
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
bit_xor(A,L,X),
adjust_flags(A,X,Y,flags(Z,S,P,_,_)),
asserta(state(regs(Y,B,C,D,E,H,L),PC,SP,flags(Z,S,P,0,0))).
op(174) :-
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
get_mem(H,L,M),
bit_xor(A,M,X),
adjust_flags(A,X,Y,flags(Z,S,P,_,_)),
asserta(state(regs(Y,B,C,D,E,H,L),PC,SP,flags(Z,S,P,0,0))).
op(175) :-
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
bit_xor(A,A,X),
adjust_flags(A,X,Y,flags(Z,S,P,_,_)),
asserta(state(regs(Y,B,C,D,E,H,L),PC,SP,flags(Z,S,P,0,0))).
op(176) :- acc_math(\/,b),!.
op(177) :- acc_math(\/,c),!.
op(178) :- acc_math(\/,d),!.
op(179) :- acc_math(\/,e),!. /* ORA E */
op(180) :- acc_math(\/,h),!. /* ORA H */
op(181) :- acc_math(\/,l),!.
op(182) :-
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
get_mem(H,L,M),
X is A \/ M,
adjust_flags(A,X,Y,flags(Z,S,P,_,_)),
asserta(state(regs(Y,B,C,D,E,H,L),PC,SP,flags(Z,S,P,0,0))).
op(183) :-
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
adjust_flags(A,A,Y,flags(Z,S,P,_,_)),
asserta(state(regs(Y,B,C,D,E,H,L),PC,SP,flags(Z,S,P,0,0))).
op(184) :- comp_regs(b),!. /* CMP B */
op(185) :- comp_regs(c),!. /* CMP C */
op(186) :- comp_regs(d),!. /* CMP D */
op(187) :- comp_regs(e),!. /* CMP E */
op(188) :- comp_regs(h),!. /* CMP H */
op(189) :- comp_regs(l),!. /* CMP L */
op(190) :- /* CMP M */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
get_mem(H,L,Q),
X is A - Q,
adjust_flags(A,X,_,Flags),
asserta(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)).
op(191) :- /* CMP A */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
adjust_flags(A,0,_,Flags),
asserta(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)).
op(192) :- /* RNZ */
(not zero_flag_is_set, return); true.
op(193) :- /* POP B */
retract(state(regs(A,_,_,D,E,H,L),PC,SP,Flags)),
get_mem(SP,C),
Hi is SP + 1,
get_mem(Hi,B),
NewSP is SP + 2,
asserta(state(regs(A,B,C,D,E,H,L),PC,NewSP,Flags)).
op(194) :- /* JNZ */
(not zero_flag_is_set, jump); carry_on.
op(195) :- /* JMP */
jump.
op(196) :- /* CNZ */
(not zero_flag_is_set, call); carry_on.
op(197) :- /* PUSH B */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)),
Hi is SP - 1,
put_mem(Hi,B),
Lo is SP - 2,
put_mem(Lo,C),
NewSP is SP - 2,
asserta(state(regs(A,B,C,D,E,H,L),PC,NewSP,Flags)).
op(198) :- /* ADI D8 */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
get_mem(PC,Q),
X is A + Q,
adjust_flags(A,X,Y,Flags),
NewPC is PC + 1,
asserta(state(regs(Y,B,C,D,E,H,L),NewPC,SP,Flags)).
op(199) :- /* RST 0 */
reset(0).
op(200) :- /* RZ */
(zero_flag_is_set, return); true.
op(201) :- /* RET */
return.
op(202) :- /* JZ */
(zero_flag_is_set, jump); carry_on.
op(204) :- /* CZ */
(zero_flag_is_set, call); carry_on.
op(205) :- /* CALL */
call.
op(206) :- /* ACI D8 */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,flags(_,_,_,CY,_))),
get_mem(PC,Q),
X is A + Q + CY,
adjust_flags(A,X,Y,Flags),
NewPC is PC + 1,
asserta(state(regs(Y,B,C,D,E,H,L),NewPC,SP,Flags)).
op(207) :- /* RST 1 */
reset(1).
op(208) :- /* RNC */
(not carry_flag_is_set, return); true.
op(209) :- /* POP D */
retract(state(regs(A,B,C_,_,H,L),PC,SP,Flags)),
get_mem(SP,E),
Hi is SP + 1,
get_mem(Hi,D),
NewSP is SP + 2,
asserta(state(regs(A,B,C,D,E,H,L),PC,NewSP,Flags)).
op(210) :- /* JNC */
(not carry_flag_is_set, jump); carry_on.
op(211) :- /* OUT */
not_implemented.
op(212) :- /* CNC */
(not carry_flag_is_set, call); carry_on.
op(213) :- /* PUSH D */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)),
Hi is SP - 1,
put_mem(Hi,D),
Lo is SP - 2,
put_mem(Lo,E),
NewSP is SP - 2,
asserta(state(regs(A,B,C,D,E,H,L),PC,NewSP,Flags)).
op(214) :- /* SUI D8 */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
get_mem(PC,Q),
X is A - Q,
adjust_flags(A,X,Y,Flags),
NewPC is PC + 1,
asserta(state(regs(Y,B,C,D,E,H,L),NewPC,SP,Flags)).
op(215) :- /* RST 2 */
reset(2).
op(216) :- /* RC */
(carry_flag_is_set, return); true.
op(218) :- /* JC */
(carry_flag_is_set, jump); carry_on.
op(219) :- /* IN */
not_implemented.
op(220) :- /* CC */
(carry_flag_is_set, call); carry_on.
op(222) :- /* SBI */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,flags(_,_,_,CY,_))),
get_mem(PC,Q),
X is A - Q - CY,
adjust_flags(A,X,Y,Flags),
NewPC is PC + 1,
asserta(state(regs(Y,B,C,D,E,H,L),NewPC,SP,Flags)).
op(223) :- /* RST 3 */
reset(3).
op(224) :- /* RPO odd parity; flag is 0 */
(not parity_flag_is_set, return); true.
op(225) :- /* POP H */
retract(state(regs(A,B,C,D,E,_,_),PC,SP,Flags)),
get_mem(SP,L),
Hi is SP + 1,
get_mem(Hi,H),
NewSP is SP + 2,
asserta(state(regs(A,B,C,D,E,H,L),PC,NewSP,Flags)).
op(226) :- /* JPO odd parity; flag is 0 */
(not parity_flag_is_set, jump); carry_on.
op(227) :- /* XTHL */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)),
get_mem(SP,NewH),
put_mem(SP,H),
SP1 is SP + 1,
get_mem(SP1,NewL),
put_mem(SP1,L),
asserta(state(regs(A,B,C,D,E,NewH,NewL),PC,SP,Flags)).
op(228) :- /* CPO odd parity; flag is 0 */
(not parity_flag_is_set, call); carry_on.
op(229) :- /* PUSH H */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)),
Hi is SP - 1,
put_mem(Hi,H),
Lo is SP - 2,
put_mem(Lo,L),
NewSP is SP - 2,
asserta(state(regs(A,B,C,D,E,H,L),PC,NewSP,Flags)).
op(230) :- /* ANI D8 */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
get_mem(PC,M),
X is A /\ M,
adjust_flags(A,X,Y,Flags),
asserta(state(regs(Y,B,C,D,E,H,L),PC,SP,Flags)).
op(231) :- /* RST 4 */
reset(4).
op(232) :- /* RPE odd parity; flag is 1 */
(parity_flag_is_set, return); true.
op(233) :- /* PCHL */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)),
decompose(PC,PCH,PCL), % (i,o,o)
decompose(NewPC,H,L), % (o,i,i)
asserta(state(regs(A,B,C,D,E,PCH,PCL),NewPC,SP,Flags)).
op(234) :- /* JPE odd parity; flag is 1 */
(parity_flag_is_set, jump); carry_on.
op(235) :- /* XCHG */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)),
asserta(state(regs(A,B,C,H,L,D,E),PC,SP,Flags)).
op(236) :- /* CPE odd parity; flag is 1 */
(parity_flag_is_set, call); carry_on.
op(238) :- /* XRI D8 */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
get_mem(PC,M),
bit_xor(A,M,X),
adjust_flags(A,X,Y,flags(Z,S,P,_,_)),
asserta(state(regs(Y,B,C,D,E,H,L),PC,SP,flags(Z,S,P,0,0))).
op(239) :- /* RST 5 */
reset(5).
op(240) :- /* RP sign flag is 0 */
(not sign_flag_is_set, return); true.
op(241) :- /* POP PSW */
retract(state(regs(_,B,C,D,E,H,L),PC,SP,_)),
get_mem(SP,Flags),
Hi is SP + 1,
get_mem(Hi,A),
NewSP is SP + 2,
S is (Flags /\ 128) / 128,
Z is (Flags /\ 64) / 64,
AC is (Flags /\ 16) / 16,
P is (Flags /\ 4) / 4,
CY is Flags /\ 1,
asserta(state(regs(A,B,C,D,E,H,L),PC,NewSP,flags(Z,S,P,CY,AC))).
op(242) :- /* JP sign flag is 0 */
(not sign_flag_is_set, jump); carry_on.
op(243) :- /* DI */
not_implemented.
op(244) :- /* CP sign flag is 0 */
(not sign_flag_is_set, call); carry_on.
op(245) :- /* PUSH PSW */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,flags(Z,S,P,CY,AC))),
Hi is SP - 1,
put_mem(Hi,A),
Lo is SP - 2,
Flags is CY * 1 + P * 4 + AC * 16 + Z * 64 + S * 128,
put_mem(Lo,Flags),
NewSP is SP - 2,
asserta(state(regs(A,B,C,D,E,H,L),PC,NewSP,flags(Z,S,P,CY,AC))).
op(246) :- /* ORI D8 */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
get_mem(PC,M),
X is A \/ M,
adjust_flags(A,X,Y,flags(Z,S,P,_,_)),
asserta(state(regs(Y,B,C,D,E,H,L),PC,SP,flags(Z,S,P,0,0))).
op(247) :- /* RST 6 */
reset(6).
op(248) :- /* RM sign flag is 1 */
(sign_flag_is_set, return); true.
op(249) :- /* SPHL */
retract(state(regs(A,B,C,D,E,H,L),PC,_,Flags)),
decompose(SP,H,L), % (o,i,i)
asserta(state(regs(A,B,C,D,E,H,L),PC,SP,Flags)).
op(250) :- /* JM sign flag is 1 */
(sign_flag_is_set, jump); carry_on.
op(251) :- /* EI */
not_implemented.
op(252) :- /* CM sign flag is 1 */
(sign_flag_is_set, call); carry_on.
op(254) :- /* CPI D8 */
retract(state(regs(A,B,C,D,E,H,L),PC,SP,_)),
get_mem(PC,Q),
X is A - Q,
adjust_flags(A,X,Y,Flags),
NewPC is PC + 1,
asserta(state(regs(A,B,C,D,E,H,L),NewPC,SP,Flags)).
op(255) :- /* RST 7 */
reset(7).
op(_) :- write('undefined opcode'), nl.
%
% end: OPS8085.ARI